Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

Abstract Low-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these to feature large-area fabrication, solution processability, high electrical performance, wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type have been achieved, the development high-performance p-type at low temperature is still limited. Here, we report a unique method synthesize tellurium nanowire networks (Te-nanonets) over area fabrication field-effect transistors (FETs) with uniform stable Maximum mobility 4.7 cm 2 /Vs, on/off current ratio 1 × 10 4 , maximum transconductance 2.18 µS achieved. To further demonstrate applicability proposed semiconductor, performance Te-nanonet-based transistor array 42 devices also measured, revealing results. Finally, broaden FETs, measurements demonstrated range, exceptionally performance.